1 tm ordering information part number temperature range screening level package 5962f9670601vec -55 o c to +125 o c mil-prf-38535 class v 16 lead sbdip 5962f9670601vxc -55 o c to +125 o c mil-prf-38535 class v 16 lead ceramic flatpack acs161d/sample 25 o c sample 16 lead sbdip acs161k/sample 25 o c sample 16 lead ceramic flatpack ACS161HMSR 25 o cdie die acs161ms radiation hardened 4-bit synchronous counter january 1996 pinouts 16 pin ceramic dual-in-line mil-std-1835, designator cdip2-t16, lead finish c top view 16 pin ceramic flatpack mil-std-1835, designator cdfp4-f16, lead finish c top view 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 cp p0 p1 p2 p3 gnd pe vcc q0 q1 q2 q3 te spe tc mr 2 3 4 5 6 7 8 116 15 14 13 12 11 10 9 mr cp p0 p1 p2 p3 pe gnd vcc tc q0 q1 q2 q3 te spe features ? devices qml qualified in accordance with mil-prf-38535 ? detailed electrical and screening requirements are contained in smd# 5962-96706 and intersil? qm plan ? 1.25 micron radiation hardened sos cmos ? total dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300k rad (si) ? single event upset (seu) immunity: <1 x 10 -10 errors/bit/day (typ) ? seu let threshold . . . . . . . . . . . . . . . . . . . . . . . >100 mev-cm 2 /mg ? dose rate upset . . . . . . . . . . . . . . . . >10 11 rad (si)/s, 20ns pulse ? dose rate survivability . . . . . . . . . . . >10 12 rad (si)/s, 20ns pulse ? latch-up free under any conditions ? military temperature range . . . . . . . . . . . . . . . . . . -55 o c to +125 o c ? significant power reduction compared to alsttl logic ? dc operating voltage range . . . . . . . . . . . . . . . . . . . . 4.5v to 5.5v ? input logic levels - vil = 30% of vcc max - vih = 70% of vcc min ? input current 1 a at vol, voh ? fast propagation delay . . . . . . . . . . . . . . . . 21ns (max), 14ns (typ) description the intersil acs161ms is a radiation hardened 4-bit binary synchronous counter. the mr is an active low master reset. spe is an active low synchronous parallel enable which disables counting and allows data at the preset inputs (p0 - p3) to load the counter. cp is the positive edge clock. tc is the terminal count or carry output. both te and pe must be high for counting to occur, but are irrelevant to loading. te low will keep tc low. the acs161ms utilizes advanced cmos/sos technology to achieve high-speed operation. this device is a member of a radiation hardened, high-speed, cmos/sos logic family. the acs161ms is supplied in a 16 lead ceramic flatpack (k suffix) or a ceramic dual-in-line package (d suffix). spec number 518818 fn3600.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
2 acs161ms functional diagram truth table operating mode inputs outputs mr cp pe te spe p n q n tc reset (clear) l x x x x x l l parallel load h x x i i l l h x x i h h (note 1) count h h h h (note 3) x count (note 1) inhibit h x i (note 2) x h (note 3) x q n (note 1) h x x i (note 2) h (note 3) x q n l h = high steady state, l = low steady state, h = high voltage level one setup time prior to the low-to-high clock transition, i = low volt- age level one setup time prior to the low-to-high clock transition, x = don?t care,q = lower case letters indicate the state of the referenced output prior to the low-to-high clock transition, = low-to-high transition. notes: 1. the tc output is high when te is high and the counter is at terminal count (hhhh). 2. the high-to-low transition of pe or te should only occur while zcp is high for conventional operation. 3. the low-to-high transition of spe should only occur while cp is high for conventional operation. 4. the tc output is high when te is high and the counter is at terminal count (hhhh). cd k cp jq qn cd k cp jq qn cd k cp jq qn cd k cp jq qn spe cp p0 mr p1 p2 p3 pe te q3 tc q2 q1 q0 spec number 518818
3 acs161ms die characteristics die dimensions: 88 mils x 88 mils 2240mm x 2240mm metallization: type: alsi metal 1 thickness: 7.125k ? 1.125k ? metal 2 thickness: 9k ? 1k ? glassivation: type: sio2 thickness: 8k ? 1k ? worst case current density: < 2.0 x 105a/cm2 bond pad size: 110mm x 110mm 4.3 mils x 4.3 mils spec number 518818
4 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com sales office headquarters north america intersil corporation 7585 irvine center drive suite 100 irvine, ca 92618 tel: (949) 341-7000 fax: (949) 341-7123 intersil corporation 2401 palm bay rd. palm bay, fl 32905 tel: (321) 724-7000 fax: (321) 724-7946 europe intersil europe sarl ave. william graisse, 3 1006 lausanne switzerland tel: +41 21 6140560 fax: +41 21 6140579 asia intersil corporation unit 1804 18/f guangdong water building 83 austin road tst, kowloon hong kong tel: +852 2723 6339 fax: +852 2730 1433 acs161ms spec number 518818 metallization mask layout acs161ms mr vcc tc (1) (16) (15) cp (2) p0 (3) p1 (4) p2 (5) p3 (6) (8) (7) (9) pe gnd spe (10) te (14) q0 (13) q1 (12) q2 (11) q3
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